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                               ANTIQUON 5978
                         SYSTEM CONTROL INTERFACE

Section 1. Pinout
----------------------------------------------------------------
The Antiquon 5978 System Control Interface comes in a DIP package with 24
pins:
                            ________
                    Vcc ---|   \/   |--- RESET
                      R ---|        |--- W
                     A0 ---|        |--- D0
                     A1 ---|        |--- D1
                     D3 ---|        |--- D2
                     D5 ---|        |--- D4
                     D7 ---|        |--- D6
                    SW0 ---|        |--- SW1
                    SW2 ---|        |--- SW3
                    SW4 ---|        |--- SW5
                    SW6 ---|        |--- SW7
                     SR ---|        |--- GND
                           '--------'

  Line(s)  I/O  Description
  ---------------------------------------------------------------------------
    D7-D0  I/O  Data: Bidirectional tri-state data bus lines, connected to
                system data bus.

    A1-A0   I   Address: Used to select the register being read or written.

      R/W   I   Read/write: Used by the system data bus to enable reading or
                writing one of the registers.

  SW7-SW0   I   Switch lines: These are read by accessing the System Switch
                Register.

       SR   O   System reset: This should be connected with the reset circuitry
                of the system.

    RESET   I   Raised to reset the 5073 PIC to its initial state.

     Vcc    I   +5VDC: Power supply connection

     GND    I   Ground: Power supply connection.

Section 2. Using the A5978
----------------------------------------------------------------
The A5978 contains four registers, selected by setting A1 and A0:

        +----+----+-----+-----------------------------------+
        | A1 | A0 | R/W | Description                       |
        +----+----+-----+-----------------------------------+
        | 0  | 0  |  R  | System switch register            |
        | 0  | 1  | R(W)| System configuration register 1   |
        | 1  | 0  | R(W)| System configuration register 2   |
        | 1  | 1  | R/W | System control port               |
        +----+----+-----+-----------------------------------+

Section 2.1. System switch register
The system switch register (register 0) gives a read-only output of the switch
lines by connecting SW0 to D0, SW1 to D1, and so forth.

Section 2.2. System configuration registers
These registers (registers 1 and 2) are single-write registers that can store a
single byte each.  They may only be written once between resets, but can be
read any number of times.  These registers are initialized to 0 at reset.

Section 2.3. System control port
The system control port contains control bits used to affect the state of the
system.  At present, only bit 0 is implemented, and causes the SR output to
raise until assertion of RESET.  Reads from this register will return 0.

Use of the 5978 in the Viejo 20

The 5978 is used to relay system configuration to application programs in the Viejo 20. The System Switch Register reads the output of switches 0 through 7, located on a DIP switch block on the motherboard. (The switch block is labeled "CONFIG"; see Fig. 9-14 in the Viejo 20 User's Manual for an illustration of the configuration jumpers and switches on the motherboard.) The System Switch Register can be read at address 0xC004.

System Configuration Register 1 is used to store the size of RAM available. This RAM is based at address 0, and the BIOS initializes Configuration Register 1 to contain the number of kilobytes (1,024 bytes) of RAM available. The maximum amount of memory available for a single-bank system is 48 KB (0x30), and for a multi-bank system is 192 KB (0xC0). System Configuration Register 1 can be accessed at address 0xC005.

System Configuration Register 2, accessible at address 0xC006, contains a set of bits that can be used by applications to determine the features present:

BitDescription
0A 1 indicates that an A5801 math coprocessor is present.
1A 1 indicates that the system supports 2 or 4 banks.
2A 1 indicates that the system supports 3 or 4 banks.
3A 1 indicates that a second floppy disk drive is present.
4A 1 indicates that a second serial interface port is present.
5A 1 indicates that a second interrupt controller is present.
Note: You need to emulate a non-banked system with two floppy disk drives, one serial interface, and one interrupt controller.

The System Control Port is used to reset the system. Writing a 1 to this port causes all devices, including the CPU and memory, to reset. This register is accessible at address 0xC007.