ANTIQUON 5602
SERIAL RECEIVER/TRANSMITTER
Section 1. Pinout
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The Antiquon 5602 Serial Receiver/Transmitter comes in a DIP package with 24
pins:
________
Vcc ---| \/ |--- RESET
R ---| |--- W
CLKOUT ---| |--- DATOUT
CLKIN ---| |--- DATIN
A0 ---| |--- D0
A1 ---| |--- D1
D3 ---| |--- D2
D5 ---| |--- D4
D7 ---| |--- D6
DTRIN ---| |--- DTROUT
CTSIN ---| |--- CTSOUT
IR ---| |--- GND
'--------'
Line(s) I/O Description
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D7-D0 I/O Data: Bidirectional tri-state data bus lines, connected to
system data bus.
A1-A0 I Address: Used to select the register being read or written.
R/W I Read/write: Used by the system data bus to enable reading or
writing one of the registers.
CLKOUT O Clock signal out. Strobed to signal that the next data bit is
ready.
CLKIN I Clock signal in. When high, a data bit is ready on DATIN.
DATOUT O Output data bit.
DATIN I Input data bit.
DTRIN I Data terminal ready, from remote device: Indicates that a
device is connected to the serial line and ready for
communication.
DTROUT O Data terminal ready, local: Indicates that this device is
connected and ready for communication.
CTSIN I Clear to send, from remote device: Indicates that this device
may send a byte across the serial line.
CTSOUT O Clear to send, local: Indicates that this device is ready to
receive data from the remote device.
IR O Interrupt request active.
RESET I Raised to reset the 5073 PIC to its initial state.
Vcc I +5VDC: Power supply connection
GND I Ground: Power supply connection.
Section 2. Using the A5602
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The A5602 contains four registers, selected by address lines A1 and A0:
+----+----+-----+-----------------------------------+
| A1 | A0 | R/W | Description |
+----+----+-----+-----------------------------------+
| 0 | 0 | R/W | Data byte register |
| 0 | 1 | R/W | Line status/control register |
| 1 | 0 | R/W | Interrupt control register |
| 1 | 1 | R/W | Scratchpad register |
+----+----+-----+-----------------------------------+
Section 2.1. Data byte register
Writing a byte to this register causes a byte to be sent across the serial
line. Reading from this register reads the most recent byte received from the
serial line.
Section 2.2. Line status/control register
This register contains a number of bits for controlling or checking line
status:
+-----+-----+---------------------------------------------------------+
| Bit | R/W | Description |
+-----+-----+---------------------------------------------------------+
| 0 | R/W | This bit is sent to the DTROUT line. |
| 1 | R | Connected to the DTRIN line. |
| 2 | R | 1 if a byte has been received and is ready for reading. |
| 3 | R | 1 if the line is clear and a byte can be sent. |
| 4 | R | 1 if the CTSIN line is high. |
| 5-7 | - | Reserved. |
+-----+-----+---------------------------------------------------------+
Section 2.3. Interrupt control register
This register is used to control generation of hardware interrupts, and
consists of the following bits:
+-----+-----+-----------------------------+
| Bit | R/W | Description |
+-----+-----+-----------------------------+
| 0 | R/W | Receive interrupt enable |
| 1 | R/W | DTR change interrupt enable |
| 2 | R/W | CTS change interrupt enable |
| 3 | R/W | Interrupt active |
| 4-7 | - | Reserved. |
+-----+-----+-----------------------------+
Setting the Receive Interrupt Enable bit to 1 causes the 5602 to assert IR when
it receives a byte from the serial line. Once IR is asserted, it may be
deasserted by clearing bit 2, the Interrupt Active bit.
Similarly, setting the DTR Change Interrupt Enable bit to 1 causes the 5602
to assert IR when the state of the DTRIN line changes from 0 to 1 or 1 to 0.
Setting the CTS Change Interrupt Enable bit to 1 causes the 5602 to assert IR
when the state of the CTSIN line changes from 0 to 1, indicating that a data
byte may be sent.
Section 2.4. Scratchpad register
This register may be used to hold a single byte of data.
There may be up to two 5602 receiver/transmitters present in a Viejo 20; the first is generally connected to a terminal device of some sort. Writing to the 5602 causes bytes to be sent to the terminal, and reading from it reads bytes input at the terminal.
The first 5602 is accessible at addresses 0xC008–0xC00B, and the second 5602 is accessible at addresses 0xC00C–0xC00F. The BIOS detects the presence of any 5602 chips at startup by using the Scratchpad Register.
To send a byte, the sender needs to ensure that the DTROUT line is raised, by setting bit 0 of the Line Status/Control Register (address 0xC009 or 0xC00D). It should wait for the DTRIN and CTSIN lines to become high (bits 1 and 4) for as long as necessary. At this point, the line should be clear and ready to send a byte, but bit 3 should be polled to ensure that this is true. The byte to send can now be written to the Data Byte Register (address 0xC008 or 0xC00C).
To receive a byte, the receiver needs to ensure that the DTROUT line is raised, by setting bit 0 of the Line Status/Control Register (address 0xC009 or 0xC00D). It should wait for the DTRIN line to become high (bit 1) for as long as necessary, then poll bit 2 until a byte has been received and the bit is set. The data byte can then be read from the Data Byte Register (address 0xC008 or 0xC00C).
The 5602 interface is connected to IR1 of the 5973 interrupt controller. If two interfaces are present, their IR lines are ORed together and connected to IR1. Interrupts may be enabled/disabled by changing bits 0–2 of the Interrupt Control Register. If an interrupt is generated, the Interrupt Active bit of both interfaces (bit 3) must be checked, and once the interrupt has been serviced, cleared.