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                               ANTIQUON 5974
                        PROGRAMMABLE INTERVAL TIMER

Section 1. Pinout
----------------------------------------------------------------
The Antiquon 5974 Programmable Interval Timer comes in a DIP package with 16
pins:
                            ________
                    Vcc ---|   \/   |--- RESET
                      R ---|        |--- W
                     IR ---|        |--- D0
                     A0 ---|        |--- D1
                    CLK ---|        |--- D2
                     D4 ---|        |--- D3
                     D6 ---|        |--- D5
                     D7 ---|        |--- GND
                           '--------'

  Line(s)  I/O  Description
  ---------------------------------------------------------------------------
    D7-D0  I/O  Data: Bidirectional tri-state data bus lines, connected to
                system data bus.

       A0   I   Address: Used to select the low or high byte of the Counter
                Register.

      R/W   I   Read/write: Used by the system data bus to enable reading or
                writing one of the registers.

      CLK   I   Clock: The counter is decremented once each time this line
                changes state from low to high.

       IR   O   Interrupt request: This line is raised when the counter reaches
                0, and lowered when the high byte of the counter value is
                written.

    RESET   I   Raised to reset the 5073 PIC to its initial state.

     Vcc    I   +5VDC: Power supply connection

     GND    I   Ground: Power supply connection.

Section 2. Programming the A5974
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The A5974 contains a 16-bit counter register which is decremented by one each
time a rising-edge clock signal is detected.  The counter may be programmed by
writing the low byte, then the high byte, selecting bytes with line A0.  The
current state of the counter may be read by reading from the two halves of the
counter.

Some system busses may allow the multiplexing of 16-bit values into two 8-bit
values; in this case, a single 16-bit read or write will access the entire
counter.  However, it must be ensured that the low byte is written first in
this event, so that interrupt acknowledgement is delayed until both bytes have
been written.

If the counter register is 0, no updates will occur, effectively disabling the
timer.  The counter register of the A5974 is initialized to 0 at reset.

Operation of the 5974 in the Viejo 20

The A5974 is a simple 16-bit counter, accessible through the 16-bit word at address 0xC002 in memory, that decrements once each time it receives a clock signal. The CLK line for the A5974 is supplied from the same clock signal used by the CPU.

Note: To emulate this, just keep a counter and decrement it once every time you execute an instruction. Precise precision isn’t precisely necessary here.

The A5974 is connected to line IR0 of the 5973 interrupt controller, which means that it generates interrupt 0 when the counter reaches 0. Once the CPU receives the timer interrupt, it should acknowledge the interrupt by loading the counter register. (To acknowledge the interrupt without starting another timeout, load the counter with 0.)