ANTIQUON 5973
                     PROGRAMMABLE INTERRUPT CONTROLLER

Section 1. Pinout
----------------------------------------------------------------
The Antiquon 5973 Programmable Interrupt Controller comes in a DIP package with
22 pins:
                            ________
                    Vcc ---|   \/   |--- RESET
                      R ---|        |--- W
                     I0 ---|        |--- D0
                     I1 ---|        |--- D1
                   IACT ---|        |--- D2
                     A0 ---|        |--- D3
                    IR0 ---|        |--- D4
                    IR1 ---|        |--- D5
                    IR2 ---|        |--- D6
                    IR3 ---|        |--- D7
                   IACK ---|        |--- GND
                           '--------'

  Line(s)  I/O  Description
  ---------------------------------------------------------------------------
    D7-D0  I/O  Data: Bidirectional tri-state data bus lines, connected to
                system data bus.

       A0   I   Address: Used to select the Interrupt Mask Register (0) or
                Interrupt Request Active Register (1).

      R/W   I   Read/write: Used by the system data bus to enable reading or
                writing one of the registers.

    I1-I0   O   Interrupt lines to the processor.  When IACT is raised, I0 and
                I1 contain the number of the active interrupt.

     IACT   O   Interrupt Active.  This is raised when an interrupt request is
                received and I1-I0 contain the number of the active interrupt.

     IACK   I   Interrupt acknowledge.  This is raised to acknowledge the most
                recent interrupt transmission via IACT/I0/I1.

    RESET   I   Raised to reset the 5073 PIC to its initial state.

     Vcc    I   +5VDC: Power supply connection

     GND    I   Ground: Power supply connection.

 IR3-IR0    I   Interrupt request activity lines.  A hardware device may raise
                one of these lines to request the interrupt (e.g., raising
                IR2 to request interrupt 2).

Section 2. Interrupt Mask Register
----------------------------------------------------------------
The Interrupt Mask Register (IMR) is selected for reading/writing by holding
pin A0 low while asserting R or W, respectively.  The IMR contains four bits,
each of which enables or disables handling of a specific interrupt.  At
power-up, all four interrupts are disabled, and the four bits of the register
are cleared to 0.

      +-----+-----------------------------------+
      | Bit |            Description            |
      +-----+-----------------------------------+
      |  0  | Enables interrupt 0 when set to 1 |
      |  1  | Enables interrupt 1 when set to 1 |
      |  2  | Enables interrupt 2 when set to 1 |
      |  3  | Enables interrupt 3 when set to 1 |
      | 4-7 | Reserved                          |
      +-----+-----------------------------------+
                  Contents of the IMR

Section 3. Interrupt Request Active Register
----------------------------------------------------------------
The Interrupt Request Active Register (IRAR) is a read-only register that gives
the states of the four interrupt request lines (IR0-IR3).  Each bit in the IRAR
is set to 1 if the corresponding IR line is high, indicating that an interrupt
request is pending.  Writes to this register are ignored.

      +-----+-------------------------+
      | Bit |       Description       |
      +-----+-------------------------+
      |  0  | Set to 1 if IR0 is high |
      |  1  | Set to 1 if IR1 is high |
      |  2  | Set to 1 if IR2 is high |
      |  3  | Set to 1 if IR3 is high |
      | 4-7 | Reserved; set to 0      |
      +-----+-------------------------+
             Contents of the IRAR

Operation of the 5973 in the Viejo 20

In the Viejo 20, the A5973 chip acts as the arbiter for devices requesting service from the CPU. Whenever a device generates an interrupt request, it raises the appropriate IR line, and the A5973 chip sends the number of the first active interrupt line to the CPU. This means that a device on interrupt line IR0 has a higher priority than one on line IR1, which is higher-priority than IR2, and so forth.

Although the A5800 CPU can support up to 16 hardware interrupts, the Viejo 20 and A5973 can only support 4. In theory, 16 interrupts could be provided by adding three more A5973s, but this isn’t necessary for current systems.

The A5973 interrupt controller is accessible by accessing addresses 0xC000 and 0xC001 in memory. Address 0xC000 accesses the IMR, and address 0xC001 accesses the IRAR.

Interrupt assignment on the Viejo 20

The interrupt lines on the Viejo 20 are assigned as follows: