ANTIQUON 5800 PROGRAMMER'S REFERENCE MANUAL

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Table of Contents
PART I: APPLICATIONS PROGRAMMING
 CHAPTER 1: INTRODUCTION TO THE A5800
   1.1. Organization of this manual
     1.1.1. Part I---Applications programming
     1.1.2. Part II---Systems programming
     1.1.3. Part III---Instruction set
   1.2. Notational conventions
     1.2.1. Data structure formats
     1.2.2. Undefined bits and software compatibility
     1.2.3. Instruction operands
     1.2.4. Hexadecimal and binary numbers

 CHAPTER 2: BASIC PROGRAMMING MODEL
   2.1. Memory organization
   2.2. Data types
   2.3. Registers
     2.3.1. General-purpose registers
     2.3.2. Pointer registers
     2.3.3. Stack implementation
     2.3.4. Status and control registers
   2.4. Instruction format
   2.5. Operand selection
   2.6. Interrupts and exceptions

 CHAPTER 3: APPLICATION INSTRUCTION SET
   3.1. Data movement instructions
   3.2. Binary arithmetic instructions
   3.3. Logical instructions
   3.4. Control transfer instructions
   3.5. Miscellaneous instructions

PART II: SYSTEMS PROGRAMMING
 CHAPTER 4: EXCEPTIONS AND INTERRUPTS
   4.1. Enabling and disabling interrupts
   4.2. Interrupt vector table
   4.3. Interrupt stack format
   4.4. Exception conditions
     4.4.1. Vector 0: Divide error
     4.4.2. Vector 1: Breakpoint
     4.4.3. Vector 2: Invalid opcode
     4.4.4. Vector 3: Coprocessor error
     4.4.5. Vector 4: System call
     4.4.6. Vector 5: Invalid address
     4.4.7. Vector 6: Instruction FC vector
     4.4.8. Vector 7: Instruction FD vector
     4.4.9. Vector 8: Instruction FE vector
     4.4.10. Vectors 9-15: Reserved
     4.4.11. Vectors 16-31: Hardware interrupts

 CHAPTER 5: PROCESSOR INITIALIZATION AND STARTUP
   5.1. Processor state after reset
   5.2. Coprocessor detection and identification

PART III: INSTRUCTION SET
 CHAPTER 6: A5800 INSTRUCTION SET
   6.1. Instruction format
   6.2. How to read the instruction descriptions
   6.3. Instruction set detail
     6.3.1. ADD: Add
     6.3.2. ADDX: Add with extension
     6.3.3. AND: Bitwise logical AND
     6.3.4. BKPT: Breakpoint instruction
     6.3.5. CALL: Call procedure
     6.3.6. CMP: Compare
     6.3.7. CPI: Coprocessor instruction
     6.3.8. CPR: Coprocessor reset
     6.3.9. CPW: Coprocessor wait
     6.3.10. DIV: Divide
     6.3.11. DSFM: Destroy stack frame
     6.3.12. HALT: Halt CPU
     6.3.13. INV: Invalid instruction
     6.3.14. ITER: Loop iteration
     6.3.15. JUMP: Jump
     6.3.16. Jcc: Conditional Jump
     6.3.17. LDAX: Load address
     6.3.18. MKFM: Make stack frame
     6.3.19. MOVE/MOVX: Move
     6.3.20. MULT: Multiply
     6.3.21. NEG: Two's complement negation
     6.3.22. NOP: No operation
     6.3.23. NOT: Bitwise logical NOT
     6.3.24. OR: Bitwise logical OR
     6.3.25. POP: Pop from stack
     6.3.26. PUSH: Push onto stack
     6.3.27. RETN: Return from procedure
     6.3.28. ROL: Rotate bits left
     6.3.29. ROLX: Rotate bits left with extension
     6.3.30. ROR: Rotate bits right
     6.3.31. RORX: Rotate bits right with extension
     6.3.32. SHL: Shift bits left
     6.3.33. SHLX: Shift bits left with extension
     6.3.34. SHR: Shift bits right
     6.3.35. SHRX: Shift bits right with extension
     6.3.36. SSHR: Signed shift bits right
     6.3.37. SUB: Subtract
     6.3.38. SUBR: Subtract reversed
     6.3.39. SUBX: Subtract with extension
     6.3.40. SYSC: System call
     6.3.41. TEST: Test bits
     6.3.42. XCHG: Exchange
     6.3.43. XOR: Bitwise logical exclusive-OR

 CHAPTER 7: OPCODE MAP

Figures
 Fig. 1-1. Data structure formatting conventions
 Fig. 2-1. Fundamental data types
 Fig. 2-2. The F register
 Fig. 3-1. The operation of SHL, SHR, SHLX, and SHRX
 Fig. 3-2. The operation of SSHR
 Fig. 3-3. Operation of ROL, ROR, ROLX, and RORX
 Fig. 4-1. Format of hardware stack during execution of handler
 Fig. 6-1. Format of register/memory selector byte
 Fig. 6-2. Format of three-register selector byte

Tables
 Table 3-1. Jump conditions
 Table 6-1. Register codes
 Table 6-2. Register/memory selector byte, bits 3-7